Various techniques exist to accomplish synchronization for data transfer between a data acquisition device and a host system. However, many of these techniques require significant amounts of hardware and/or software to achieve synchronization. Additional factors to consider are the characteristics of the A/D converter utilized in the acquisition device. In the embodiment illustrated for the present invention, A/D converters are utilized in an electrocardiography (EKG) pod. In this context, the term "pod" refers to a data acquisition device coupled to a medical patient for acquiring EKG signals from the patient, and the term "host" refers to a signal processing and display device which is remote from the pod and forms the remainder portion of a physiological signal patient monitor.
It would be desirable to use sigma-delta A/D converters in the pod to acquire and sample the EKG signals because they have several desirable characteristics: high resolution can be achieved with relatively low cost as compared to sample and hold A/D converters, sigma-delta A/D converters have built in filtering that can reduce 50-60 Hz noise, as well as provide low-pass filtering of the input signal. Furthermore, by choosing the appropriate A/D clock input, any sample rate can be achieved. Additionally, since the A/D converter sample update rate is controlled completely by the A/D clock and not by external data requests, as is the case with a sample and hold A/D converter, sample-to-sample jitter is eliminated.
However, sigma-delta A/D converters have some operating characteristics that need consideration in order that a host system can properly acquire data from them.
Sigma-delta A/D converters are free running, and therefore provide samples at a rate defined by the A/D clock signal. If this clock signal is not derived from the same clock associated with the host system, the rate at which the A/D converter supplies samples will not be the same as the rate at which the host system requests the samples. Samples supplied to the host will be either lost or repeated, depending upon which part of the system has a faster clock. Additionally, when the A/D samples are representative of a sequence of a plurality of different signals whose samples are periodically provided (or updated) by the acquisition device, the periodic updating is generally not done at a time that is "aligned" with the sample requests from the host system for those A/D samples.
Considering the rate problem first, if, for example, the host system sample clock is running slightly faster than the A/D sample update clock, occasionally an A/D sample will be repeated because the host input port is acquiring samples faster than the pod A/D converter can provide new ones. Conversely, if the A/D sampling clock is running slightly faster than the host system sample clock, occasionally a sample will be lost because the pod A/D converter will be providing samples faster than the host input port can acquire them.
These lost or repeated samples result in a discontinuity in the sampled waveform of the acquired signals, e.g., EKG signals. The discontinuity creates added frequency harmonics in the waveform. When software filtering is performed on the acquired waveform, these frequency harmonics may create ringing in the filter output signal. The effects of the ringing and extra frequency harmonics can be reduced somewhat by software changes to the filter characteristics, such as the size of the sampling window and the filter cutoff parameters, but this ringing effect cannot be easily eliminated. Therefore, the filter output waveform has a substantially reduced signal-to-noise ratio, as well as other undesirable characteristics, such as the added harmonics.
One solution to this problem is to allow the host system to sample at a rate slightly faster than the A/D sample update rate. This technique means that occasionally a sample will be repeated. However, if this condition can be detected, the host system can just discard the extra sample and continue. This technique requires special hardware and software to determine that a repeated sample has been read by the host system. This can add cost/complexity to the system, but isn't a significant problem. However, this solution only works well in a system that is data driven, but not in a real-time environment where the host system and acquired data are time driven. In a real-time system, data is being acquired at real time, and even if a repeated sample is detected and discarded, a "hole" in time occurs, and a discontinuity will result. Thus, this technique is not suitable for a real-time data acquisition system such as a patient monitor.
Alternatively, clock synchronization can be achieved by using the same master clock for both the A/D converter in the pod and the pod communication interface to the host. However, this technique may not be available, for example, if the frequency requirements for the pod interface and the A/D converters are different. Secondly, provisions must be made to transmit the host clock frequency to the pod. Any provisions to add a clock signal conductor will undesirably add cost to the system because extra wires and isolation will have to be added to the cable/connector between the pod and the host system.
A second method for synchronizing the two non-synchronous clocks is to employ a conventional phase-locked loop (PLL) arrangement, well known by those of ordinary skill in this technology, wherein one clock signal is used as a master clock, and the other clock signal is produced by applying the DC output signal of the PLL to a voltage controlled oscillator (VCO). The VCO produces an output signal that is frequency locked to the master clock signal. Although PLL components are commercially available, but are expensive, have significant power requirements, and utilize significant circuit board area, all factors which may adversely affect the pod design.
It would be desirable to eliminate the difficulties presented by this synchronization error by providing a method to synchronize the rate of a host system clock with the A/D sampling clock of a remote data acquisition device that provides sampled data to the host system.
The second problem, as previously noted, is to synchronize or "align" the timing of the A/D converter sample updates, so that a given A/D sample of a sequence of a plurality of samples that are developed by the A/D converter is provided to the data communication link at exactly the same time at which the host system requests the given A/D sample, a so-called "just-in-time" data transfer technique. Without such alignment the pod would require data storage, such as a buffer memory, to hold the plurality of samples until they are requested by the host. Addition of such data storage to the pod is undesirable because it increases the size, weight, and power consumption of the pod.
Alignment of host system sample requests with a given A/D sample from the pod can be accomplished, for example, by using an interrupt to signal the host system when the requested sample is ready. However, this technique cannot be used in a system that is not tightly coupled. Where the link between the remote pod and the host system is via a serial interface, the host system is not tightly coupled to the remote pod A/D converter. If the host microprocessor is not tightly coupled to the pod, there will be some latency (delay) associated with when the interrupt occurs vs. when the host microprocessor can actually read the sample from the A/D. Thus, unless the host can immediately request and receive the sample from the A/D when it is ready, e.g., the A/D converter output is directly readable by the host icroprocessor via a simple read instruction, then it can ake a while before the host can actually request the sample indicated as ready and respond to the interrupt. Due to this latency it is highly likely that by the time the host responds to the interrupt and actually reads the sample, the next sample from the A/D is ready, and alignment will be lost. An additional disadvantage of an interrupt driven system is that the host system must respond immediately to the interrupt or the sample update will be lost. This can burden the host system to the point that it prevents the host system from performing other vital real-time tasks.
Alternatively, the host system can poll the A/D system in the pod (e.g., look for a "ready" flag) to determine when the A/D samples are ready, and then request the data. A polling technique also has several drawbacks. Firstly, a significant burden is placed on the host to periodically poll the pod to determine when the samples are ready. This polling technique requires so much processing in a real-time system that it is only effective at very low sample rates. Secondly, there is always a lag between when the A/D system indicates a sample is ready versus when the host system actually requests the data. If this lag becomes too great, A/D samples will be lost because the host does not have time to read all of the A/D data before the next A/D sample update occurs.
The host system can try to align its requests for the A/D samples with when the A/D samples are developed and ready for being provided to the communication link. This technique works well if the A/D samples are occurring at regular intervals. However, this technique significantly increases the amount of processor overhead required by the host to determine when to start the A/D converters, then poll the A/D's at a high rate to determine when a given A/D sample is ready, and finally to "lock onto the A/D samples" in order to align the host's sample requests with when the remote pod's A/D samples are ready. This software based "locking and aligning" technique is further complicated by the fact that the only method of polling a remote pod is via it's communication link, which may be a bandwidth limited serial link, thereby making it difficult to determine precisely when the remote A/D converters produced a sample. Thus, there will be an ambiguity between when a given A/D sample is actually developed, and when the host system will be able to check the A/D ready flag. This ambiguity could result in a lost sample unless special considerations are taken.
Alternatively, a FIFO shift register or buffer can be added to the system. This technique allows the A/D converter in the pod to load the FIFO with the newly developed, i.e., updated, samples, and allows the host system to read these samples when it is ready. This technique does not require the host system requests for reading an A/D sample to be exactly aligned with when each A/D sample update occurs. No data will be lost as long as the host system reads the data at least as fast as the remote pod A/D sample updates occur. Although this technique works well, it results in a significant hardware cost increase for the hardware interface.
All of the above techniques can be used to align the remote pod sample updates with the host system requests, but none are optimal. Each technique either adds complexity to the host system hardware interface and/or its software in order to align the samples.
It would be desirable to synchronize the A/D sample updates to exactly correspond in time with the host sample requests, a kind of "just in time" technique, with minimum increase in complexity of either of the system hardware or software.
Finally, once the host/pod system is locked, data will be properly acquired from the remote pod by the host system. However, the above-described "locking and aligning" techniques require that the sample requests being received from the host system via the serial link are valid.
In any remote system connected via a communications link, the possibility exists that the integrity of the link will be broken. An invalid or lost sample request signal would result in missed A/D samples. Additionally, it is possible that the sample update rate of the A/D converters could change, or even fail completely. In these situations, it is essential that the failure mode be detected so the host system is notified of the error, and can then recover.
It would be desirable to provide a simple mechanism that would recognize an error condition after synchronization has been established, and upon such recognition, re-establish synchronization with a minimum increase in complexity of either of the system hardware or software.